The invention relates to the design and analysis of integrated circuits, and more specifically, to methods and systems for performing a hierarchical visualization-based analysis of integrated circuits.
The age of information and electronic commerce has been made possible by the development of electronic circuits and their miniaturization through integrated circuit technology. Integrated circuits are sometimes referred to as “chips.” To meet the challenges of building more complex and higher performance integrated circuits, software tools are used. These tools are in an area commonly referred to as computer aided design (CAD), computer aided engineering (CAE), or electronic design automation (EDA). There is a constant need to improve these electronic automatic tools in order to address the desire for higher integration and greater complexity, and better performance in integrated circuits.
In nanoscale integrated circuit technology, a large and complex circuit is challenging to design. The circuit can be strongly impacted by nanoscale process variations and nanoscale materials or device physics limitations.
Software tools can be used to design and verify a layout of an integrated circuit. Currently, software tools provide a top-down two-dimensional (2D) layout of an integrated circuit. In a 2D layout, overlayers typically hide underlayers. This complicates an engineer's task of viewing and interpreting cause and effect contextually when overlayers are made transparent or hidden.
Therefore, what is needed is a system and technique to enable visualization, isolation, and interpretation of localized electrical effects of integrated circuits.